Phase-shifted zero-voltage-transition (PS-ZVT) full bridge converter circuits eliminate switching losses and substantially decrease electromagnetic interference (EMI) by utilizing the effects of parasitic capacitance in switching devices such as MOSFETs and IGBTs in conjunction with parasitic and/or additional inductance to ensure that the switching devices each transition to a conductive state when the switched voltage is essentially zero. See, for example, the U.S. Pat. No. 4,864,479 to Steigerwald et al., incorporated by reference herein.
One example of a prior art full bridge DC-DC transistor converter is shown in FIG. 1. The MOSFET transistors Q1, Q2, Q3 and Q4 define the legs of the bridge circuit, and diagonally opposed transistor pairs are alternately gated on and off to establish an AC current in the primary winding T1 of a center-tapped transformer T using input voltage Vbus. The center-tap of transformer T is grounded, and the secondary windings T2 and T3 are coupled to a common node N through diodes D5 and D6. The voltage at node N is filtered by an LC filter comprising the series combination of inductor Lf and capacitor Cf, and the capacitor voltage Vc(t) is applied to a resistive load RL. Each transistor Q1, Q2, Q3, Q4 is depicted as including a diode D1, D2, D3, D4 (which may be the transistor body diode) and a parasitic output capacitance C1, C2, C3 and C4, both connected in parallel with the current-carrying path of the respective transistor.
Once the diagonally opposed transistors Q1 and Q4 are gated on to establish primary winding current in the direction of arrow A, the winding current can be reversed through a resonant transition with zero voltage at transistor turn-on. First, transistor Q4 is gated off, and the primary winding current free-wheels through transistor Q1 and the output capacitances C3 and C4, charging capacitance C4 and discharging capacitance C3. Once capacitance C3 has been discharged, diode D3 becomes forward biased and continues to carry the free-wheeling current. Also, transistor Q3 is gated on at the zero-voltage transition, and the free-wheeling current flows through both diode D3 and the source-to-drain circuit of transistor Q3. When transistor Q1 is gated off, the free-wheeling current charges capacitance C1 and discharges capacitance C2. Once capacitance C2 is discharged, transistor Q2 can be gated on with a zero-voltage transition, the primary winding current in the direction of arrow B flows through transistors Q2 and Q3. The next transition occurs when transistor Q3 is gated off, transistor Q4 is gated on at zero voltage to share the free-wheeling current with diode D4, and transistor Q1 is gated on at zero voltage to complete the transition.
One factor to be considered in the design of a PS-ZVT converter is the transistor power dissipation, particularly since the transistors that conduct the entire free-wheeling current (Q1 and Q2 in the above example) dissipate more power than the transistors (Q3 and Q4) that share the free-wheeling current with a free-wheeling diode. In an actual converter circuit based on FIG. 1, for example, the average power dissipation of transistors Q1 and Q2 is 33 W, while the average power dissipation of transistors Q3 and Q4 is 19 W. The imbalance could be even more pronounced in the case of bipolar transistors such as IGBTs because they cannot conduct in reverse to share the free-wheeling current. Since convenience and economy usually dictate the use of identical devices for each bridge transistor, the selected devices must be designed to tolerate the maximum power dissipation, 33 W in this case. It would clearly be more cost effective if identical lower-wattage devices could be used in place of the higher-wattage devices.